Ruben Undheim a8200a773f A few modifications after pull request comments ...

- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h

2016-06-18 14:23:38 +02:00

..

ast

A few modifications after pull request comments

2016-06-18 14:23:38 +02:00

blif

Added $sop cell type and "abc -sop"

2016-06-17 13:50:09 +02:00

ilang

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

liberty

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

verific

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

verilog

Added support for SystemVerilog packages with localparam definitions

2016-06-18 10:53:55 +02:00

vhdl2verilog

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00