Eddie Hung bb2144ae73 Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime ...

Error out if -abc9 and -retime specified

2019-07-10 14:38:13 -07:00

..

tests

Improved xilinx "bram1" test

2015-04-09 17:12:12 +02:00

.gitignore

Added support for initialized xilinx brams

2015-04-06 17:07:10 +02:00

abc_xc7_nowide.lut

Add _nowide variants of LUT libraries in -nowidelut flows

2019-06-26 10:23:29 -07:00

abc_xc7.box

Fix $__XILINX_MUXF78 box timing

2019-07-01 14:04:06 -07:00

abc_xc7.lut

Simplify comment

2019-06-17 19:14:41 -07:00

arith_map.v

Instead of MUXCY/XORCY use CARRY4 (with timing)

2019-05-21 16:19:45 -07:00

brams_bb.v

Remove WIP ABC9 flop support

2019-06-14 10:37:52 -07:00

brams_init.py

Squelch trailing whitespace, including meta-whitespace

2018-03-11 16:03:41 +01:00

brams_map.v

Revert BRAM WRITE_MODE changes.

2019-03-04 09:22:22 -08:00

brams.txt

Added read-enable to memory model

2015-09-25 12:23:11 +02:00

cells_map.v

Add some spacing

2019-07-10 12:32:33 -07:00

cells_sim.v

Revert "Fix broken MUXFx box, use MUXF7x2 box instead"

2019-07-01 14:01:09 -07:00

cells_xtra.sh

Merge remote-tracking branch 'origin/master' into xaig

2019-06-25 09:33:11 -07:00

cells_xtra.v

Merge remote-tracking branch 'origin/master' into xaig

2019-06-25 09:33:11 -07:00

drams_map.v

Add RAM32X1D support

2019-06-24 16:16:50 -07:00

drams.txt

Add RAM32X1D support

2019-06-24 16:16:50 -07:00

ff_map.v

Cleanup

2019-06-05 12:28:46 -07:00

lut_map.v

Really permute Xilinx LUT mappings as default LUT6.I5:A6

2019-06-18 11:48:48 -07:00

Makefile.inc

Merge remote-tracking branch 'origin/master' into xc7mux

2019-06-29 19:39:27 -07:00

mux_map.v

Change synth_xilinx's -nomux to -minmuxf <int>

2019-06-24 10:04:01 -07:00

synth_xilinx.cc

Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime

2019-07-10 14:38:13 -07:00