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a8cdcb3dd2f6c0c514008ff83ccad2a4e51ec641
YosysHQ.yosys
/
frontends
/
verilog
History
Clifford Wolf
fe829bdbdc
Added log_warning() API
2014-11-09 10:44:23 +01:00
..
.gitignore
Updated .gitignore file for ilang and verilog frontends
2014-10-15 01:14:38 +02:00
const2ast.cc
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Makefile.inc
Updated lexers & parsers to include prefixes
2014-10-15 00:48:19 +02:00
preproc.cc
Re-introduced Yosys::readsome() helper function
2014-10-23 10:58:36 +02:00
verilog_frontend.cc
Print "SystemVerilog" in "read_verilog -sv" log messages
2014-10-16 10:31:54 +02:00
verilog_frontend.h
Changed frontend-api from FILE to std::istream
2014-08-23 15:03:55 +02:00
verilog_lexer.l
Added log_warning() API
2014-11-09 10:44:23 +01:00
verilog_parser.y
Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
2014-10-30 14:01:02 +01:00