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a90d1b5d5ee6f7f1abf72b6a146b43411c6dbcda
YosysHQ.yosys
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techlibs
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intel
History
Emil J. Tywoniak
42e01aa1ca
intel: register bram celltypes
2026-04-02 17:01:32 +02:00
..
common
Fixed data/address width parameters
2024-03-06 02:45:07 +01:00
cyclone10lp
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneiv
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneive
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
max10
Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
Makefile.inc
synth_intel: Remove incomplete Arria 10 GX support.
2020-08-21 01:46:06 +02:00
synth_intel.cc
intel: register bram celltypes
2026-04-02 17:01:32 +02:00
