Eddie Hung 65924fd12f Test *.aag too, by using *.aig as reference

2019-06-07 11:28:05 -07:00

..

aiger

Test *.aag too, by using *.aig as reference

2019-06-07 11:28:05 -07:00

asicworld

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00

bram

Added support for (single-clock) transparent memories to bram tests

2016-11-01 10:03:13 +01:00

errors

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

fsm

Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.

2016-09-22 11:49:29 -06:00

hana

Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.

2016-09-22 11:49:29 -06:00

liberty

Liberty file parser now accepts superfluous ;

2019-03-27 15:16:19 +01:00

lut

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

memories

Fix #938 - Crash occurs in case when use write_firrtl command

2019-05-01 13:16:01 -07:00

opt

Fix WREDUCE on FF not fixing ARST_VALUE parameter.

2019-02-22 10:30:42 -08:00

realmath

Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.

2016-09-22 11:49:29 -06:00

sat

support repeat loops with constant repeat counts outside of constant functions

2019-04-09 12:28:32 -04:00

share

Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.

2016-09-22 11:49:29 -06:00

simple

Rename implicit_ports.sv test to implicit_ports.v

2019-06-07 13:12:25 +02:00

smv

Progress in SMV back-end

2015-06-19 14:08:46 +02:00

sva

Fix "verific -extnets" for more complex situations

2019-03-26 14:17:46 +01:00

svinterfaces

Fix typo in tests/svinterfaces/runone.sh

2019-05-03 14:40:51 +02:00

techmap

Added read-enable to memory model

2015-09-25 12:23:11 +02:00

tools

Use ABC to convert from AIGER to Verilog

2019-06-07 11:06:57 -07:00

unit

Build hotfix in tests/unit/Makefile

2016-12-11 10:58:49 +01:00

various

Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983

2019-06-07 12:08:42 +02:00

vloghtb

bugfix in blif front-end

2015-05-18 11:15:49 +02:00