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acf3f5694bb0cd9911566855df27c17e7e82b8cc
YosysHQ.yosys
/
techlibs
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xilinx
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Keith Rothman
1f9235ede5
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
...
Signed-off-by: Keith Rothman <
537074+litghost@users.noreply.github.com
>
2019-04-12 09:35:15 -07:00
..
tests
…
.gitignore
…
arith_map.v
…
brams_bb.v
…
brams_init.py
…
brams_map.v
Revert BRAM WRITE_MODE changes.
2019-03-04 09:22:22 -08:00
brams.txt
…
cells_map.v
…
cells_sim.v
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
2019-04-12 09:35:15 -07:00
cells_xtra.sh
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
2019-04-12 09:35:15 -07:00
cells_xtra.v
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
2019-04-12 09:35:15 -07:00
drams_map.v
…
drams.txt
…
ff_map.v
…
lut_map.v
…
Makefile.inc
…
synth_xilinx.cc
Add Xilinx negedge FFs to synth_xilinx dffinit call,
fixes
#873
2019-03-19 20:30:28 +01:00
