Clifford Wolf 5c6247dfa6 Add support for SVA sequence concatenation ranges via verific ...

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2018-02-18 16:35:06 +01:00

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ast

Add support for "yosys -E"

2018-01-07 16:36:13 +01:00

blif

Increase maximum LUT size in blifparse to 12 bits

2017-09-27 15:27:42 +02:00

ilang

Added avail params to ilang format, check module params in 'hierarchy -check'

2016-10-22 11:05:49 +02:00

json

Parse reals as string in JSON front-end

2017-09-26 14:37:03 +02:00

liberty

Improve handling of "bus" pins in liberty front-end (some files use bus.pin.direction)

2018-02-15 17:36:08 +01:00

verific

Add support for SVA sequence concatenation ranges via verific

2018-02-18 16:35:06 +01:00

verilog

Add support for "yosys -E"

2018-01-07 16:36:13 +01:00