This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-02-11 19:04:33 +00:00
Code
Issues
Releases
Wiki
Activity
Files
b0c71ed5945716e5719c09f73f056fc6a4834042
YosysHQ.yosys
/
techlibs
/
common
History
Marcelina Kościelnicka
93508d58da
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
..
.gitignore
…
abc9_map.v
…
abc9_model.v
…
abc9_unmap.v
…
adff2dff.v
…
cellhelp.py
…
cells.lib
…
cmp2lcu.v
…
cmp2lut.v
…
dff2ff.v
…
gate2lut.v
…
gen_fine_ffs.py
Add $aldff and $aldffe: flip-flops with async load.
2021-10-02 18:12:52 +02:00
Makefile.inc
…
mul2dsp.v
Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
pmux2mux.v
…
prep.cc
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
simcells.v
Add $aldff and $aldffe: flip-flops with async load.
2021-10-02 18:12:52 +02:00
simlib.v
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
synth.cc
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
techmap.v
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00