Krystine Sherwin e40134c856

Docs: Update for properties ...

Add properties page, move cell_gate and cell_word under a singular cell_index along with properties.  Fix links accordingly.

Also drop x-aware and x-output todos since they are resolved.

2024-10-15 07:35:41 +13:00

..

APPNOTE_010_Verilog_to_BLIF.rst

docs: more tidying

2023-11-16 09:46:47 +13:00

APPNOTE_012_Verilog_to_BTOR.rst

Replace 010 and 012 with pdf

2023-10-30 10:34:30 +13:00

auxlibs.rst

Docs: Shorten cmd:ref

2024-10-15 07:22:04 +13:00

auxprogs.rst

Docs: Rename source/temp to source/generated

2024-04-15 10:13:22 +12:00

env_vars.rst

Docs: Shorten cmd:ref

2024-10-15 07:22:04 +13:00

primer.rst

Docs: Apply invert-helper where needed

2024-05-11 10:40:54 +12:00

rtlil_text.rst

Docs: Update for properties

2024-10-15 07:35:41 +13:00