github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-04 07:10:19 +00:00
Code Issues Releases Wiki Activity
Files
b232e027bf18bd37206c15209e23d2f8f7b2a17d
YosysHQ.yosys/frontends/verilog
History
Clifford Wolf 41b843c27b Un-break default specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Convert more log_error() to log_file_error() where possible.
2018-07-20 09:37:44 -07:00
Makefile.inc
Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
2019-03-29 16:32:44 +01:00
preproc.cc
Support SystemVerilog `` extension for macros
2018-05-17 00:09:56 -04:00
verilog_frontend.cc
Add specify parser
2019-04-23 21:36:59 +02:00
verilog_frontend.h
Add specify parser
2019-04-23 21:36:59 +02:00
verilog_lexer.l
Un-break default specify parser
2019-04-23 21:36:59 +02:00
verilog_parser.y
Add specify parser
2019-04-23 21:36:59 +02:00