whitequark 3bffd09d64 Merge pull request #2006 from jersey99/signed-in-rtlil-wire ...

Preserve 'signed'-ness of a verilog wire through RTLIL

2020-06-04 11:23:06 +00:00

..

.gitignore

Add "make coverage"

2018-08-27 14:22:21 +02:00

ilang_frontend.cc

Add "read_ilang -lib"

2019-04-05 17:31:49 +02:00

ilang_frontend.h

Add "read_ilang -lib"

2019-04-05 17:31:49 +02:00

ilang_lexer.l

ilang_lexer: fix check for out of range literal.

2020-05-29 06:58:44 +00:00

ilang_parser.y

Merge pull request #2006 from jersey99/signed-in-rtlil-wire

2020-06-04 11:23:06 +00:00

Makefile.inc

Add "make coverage"

2018-08-27 14:22:21 +02:00