Clifford Wolf 91dd87e60b Improved scope resolution of local regs in Verilog+AST frontend

2014-08-05 12:15:53 +02:00

..

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00

const2ast.cc

Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

2014-07-31 13:19:47 +02:00

lexer.l

Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

2014-07-31 13:19:47 +02:00

Makefile.inc

Added "make PRETTY=1"

2014-07-24 17:15:01 +02:00

parser.y

Improved scope resolution of local regs in Verilog+AST frontend

2014-08-05 12:15:53 +02:00

preproc.cc

Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

2014-07-31 13:19:47 +02:00

verilog_frontend.cc

Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

2014-07-31 13:19:47 +02:00

verilog_frontend.h

Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

2014-07-31 13:19:47 +02:00