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b567f03c266b0c44d81a24dde2ed538f1db05d4e
YosysHQ.yosys
/
frontends
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verilog
History
Claire Wolf
a7cc4673c3
Fix partsel expr bit width handling and add test case
...
Signed-off-by: Claire Wolf <
claire@symbioticeda.com
>
2020-03-08 16:12:12 +01:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Fix handling of z_digit "?" and fix optimization of cmp with "z"
2019-09-13 13:39:39 +02:00
Makefile.inc
Read bigger Verilog files.
2019-05-18 14:20:30 +03:00
preproc.cc
Fixed some missing "verilog_" in documentation
2019-12-13 10:17:05 -03:00
verilog_frontend.cc
Closes
#1717
. Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
verilog_frontend.h
Closes
#1717
. Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
verilog_lexer.l
Closes
#1717
. Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
verilog_parser.y
Fix partsel expr bit width handling and add test case
2020-03-08 16:12:12 +01:00
