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YosysHQ.yosys/passes
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Eddie Hung b66c99ece0 Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext 
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
2019-09-18 12:40:08 -07:00
..
cmds
Revert "SigSet<Cell*> to use stable compare class"
2019-09-13 09:49:15 -07:00
equiv
Add equiv_opt -multiclock
2019-09-11 13:55:59 +01:00
fsm
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
hierarchy
Adopt @cliffordwolf's suggestion
2019-09-03 12:18:50 -07:00
memory
stoi -> atoi
2019-08-07 11:09:17 -07:00
opt
Revert "SigSet<Cell*> to use stable compare class"
2019-09-13 09:49:15 -07:00
pmgen
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
2019-09-18 12:40:08 -07:00
proc
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
sat
Revert "SigSet<Cell*> to use stable compare class"
2019-09-13 09:49:15 -07:00
techmap
Explicitly order function arguments
2019-09-13 16:18:05 -07:00
tests
More use of IdString::in()
2019-08-15 09:23:57 -07:00