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b678b15c6d0d14580ca18e89f86926eabf8fead0
YosysHQ.yosys
/
tests
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arch
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Eddie Hung
ae619ba87a
Add
#1626
testcase
2020-01-12 15:21:26 -08:00
..
anlogic
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
common
Merge pull request
#1574
from YosysHQ/eddie/xilinx_lutram
2019-12-16 21:48:21 -08:00
ecp5
Add testcase from
#1459
2020-01-06 16:22:22 -08:00
efinix
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
gowin
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
ice40
Add
#1626
testcase
2020-01-12 15:21:26 -08:00
xilinx
Combine tests to check multiple clock domains
2020-01-02 14:38:59 -08:00
run-test.sh
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00
