Clifford Wolf f01a61f093 Rename implicit_ports.sv test to implicit_ports.v ...

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2019-06-07 13:12:25 +02:00

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.gitignore

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aes_kexp128.v

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always01.v

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always02.v

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always03.v

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arraycells.v

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arrays01.v

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attrib01_module.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib02_port_decl.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib03_parameter.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib04_net_var.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib05_port_conn.v.DISABLED

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib06_operator_suffix.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib07_func_call.v.DISABLED

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib08_mod_inst.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

attrib09_case.v

Added tests for attributes

2019-06-03 09:25:20 +02:00

carryadd.v

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constmuldivmod.v

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constpower.v

Fixed handling of power operator

2013-11-07 22:20:00 +01:00

dff_different_styles.v

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dff_init.v

Add test case from #997

2019-05-07 19:58:04 +02:00

fiedler-cooley.v

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forgen01.v

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forgen02.v

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forloops.v

Add additional test cases for for-loops

2019-05-01 09:32:07 +02:00

fsm.v

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generate.v

fix local name resolution in prefix constructs

2019-03-18 20:43:20 -04:00

graphtest.v

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hierarchy.v

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hierdefparam.v

Fix handling of defparam for when default_nettype is none

2019-02-24 20:09:41 +01:00

i2c_master_tests.v

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implicit_ports.v

Rename implicit_ports.sv test to implicit_ports.v

2019-06-07 13:12:25 +02:00

localparam_attr.v

Added tests for Verilog frontent for attributes on parameters and localparams

2019-05-16 12:53:43 +02:00

loops.v

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macros.v

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mem2reg.v

Add splitcmplxassign test case and silence splitcmplxassign warning

2019-05-01 10:01:54 +02:00

mem_arst.v

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memory.v

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multiplier.v

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muxtree.v

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omsp_dbg_uart.v

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operators.v

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param_attr.v

Added tests for Verilog frontent for attributes on parameters and localparams

2019-05-16 12:53:43 +02:00

paramods.v

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partsel.v

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peepopt.v

Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047

2019-05-28 17:17:56 +02:00

process.v

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realexpr.v

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repwhile.v

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retime.v

Add retime test

2019-04-05 16:28:46 -07:00

rotate.v

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run-test.sh

SystemVerilog support for implicit named port connections

2019-06-06 18:07:49 +02:00

scopes.v

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signedexpr.v

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sincos.v

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specify.v

Fix tests/simple/specify.v

2018-03-27 14:34:00 +02:00

subbytes.v

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task_func.v

Fix handling of task output ports in clocked always blocks, fixes #857

2019-03-07 22:44:37 -08:00

undef_eqx_nex.v

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usb_phy_tests.v

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values.v

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vloghammer.v

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wandwor.v

Add actual wandwor test that is part of "make test"

2019-05-28 16:42:50 +02:00

wreduce.v

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xfirrtl

Fix #938 - Crash occurs in case when use write_firrtl command

2019-05-01 13:16:01 -07:00