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YosysHQ.yosys/backends
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whitequark ba11060e59 cxxrtl: factor out -noproc/-noflatten from -O. 
Although these options can be thought of as optimizations, they are
essentially orthogonal to the core of -O, which is managing signal
buffering and scope. Going from -O4 to -O2 means going from limited
to complete design visibility, yet in both cases proc and flatten
are desirable.
2020-06-09 20:18:07 +00:00
..
aiger
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
2020-06-04 08:15:25 -07:00
blif
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
btor
btor backend: make not printing internal names default
2020-06-04 16:24:16 +02:00
cxxrtl
cxxrtl: factor out -noproc/-noflatten from -O.
2020-06-09 20:18:07 +00:00
edif
Improve net priorities in EDIF back-end
2020-04-21 12:35:25 +02:00
firrtl
Add flooring modulo operator
2020-05-28 22:59:03 +02:00
ilang
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-04-27 09:44:24 -07:00
intersynth
Clean up pseudo-private member usage in backends/intersynth/intersynth.cc.
2020-04-01 06:32:09 +00:00
json
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-04-27 09:44:24 -07:00
protobuf
Add aiger and protobuf backends binary support
2019-09-28 09:51:48 +02:00
simplec
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
smt2
more reasonable numbers for memory
2020-06-04 17:00:04 -04:00
smv
Add flooring division operator
2020-05-28 22:59:04 +02:00
spice
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
table
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
verilog
Add flooring division operator
2020-05-28 22:59:04 +02:00