22 lines
281 B
Plaintext
22 lines
281 B
Plaintext
read_verilog << EOF
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module mod_and_or (
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input a,
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input b,
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input c,
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input d,
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output reg y
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);
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always @(a,b,c,d) begin
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y <= (a&b)|(c&d);
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end
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endmodule
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EOF
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hierarchy -top mod_and_or
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proc
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opt
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techmap -map ./bug3515.v
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proc
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extract -map ./bug3515.v -verbose
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proc
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