Eddie Hung 076af2e617 Missing newline

2019-08-20 20:37:52 -07:00

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.gitignore

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adff2dff.v

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cellhelp.py

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cells.lib

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cmp2lut.v

gen_lut to return correctly sized LUT mask

2019-07-16 12:45:29 -07:00

dff2ff.v

Add dff2ff.v techmap file

2017-05-31 11:45:58 +02:00

gate2lut.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

Makefile.inc

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

pmux2mux.v

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prep.cc

Add "wreduce -keepdc", fixes #1016

2019-05-20 15:36:13 +02:00

simcells.v

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

2019-08-06 04:47:55 +02:00

simlib.v

Reformat so it shows up/looks nice when "help $alu" and "help $alu+"

2019-08-09 12:33:39 -07:00

synth.cc

Missing newline

2019-08-20 20:37:52 -07:00

techmap.v

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