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bb2d5bc4f85ac95104fbd2591ad92ebf0c22e11d
YosysHQ.yosys
/
techlibs
/
common
History
Eddie Hung
076af2e617
Missing newline
2019-08-20 20:37:52 -07:00
..
.gitignore
…
adff2dff.v
…
cellhelp.py
…
cells.lib
…
cmp2lut.v
gen_lut to return correctly sized LUT mask
2019-07-16 12:45:29 -07:00
dff2ff.v
…
gate2lut.v
…
Makefile.inc
…
pmux2mux.v
…
prep.cc
Add "wreduce -keepdc",
fixes
#1016
2019-05-20 15:36:13 +02:00
simcells.v
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
2019-08-06 04:47:55 +02:00
simlib.v
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"
2019-08-09 12:33:39 -07:00
synth.cc
Missing newline
2019-08-20 20:37:52 -07:00
techmap.v
…