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YosysHQ.yosys/techlibs/xilinx
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Eddie Hung bbab608691 Remove SRL* delays from cells_sim.v
2019-08-20 18:14:40 -07:00
..
tests
…
.gitignore
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abc_map.v
LUTMUX -> LUTMUX6
2019-08-20 18:08:07 -07:00
abc_model.v
Wrap SRL{16,32} too
2019-08-20 15:09:38 -07:00
abc_unmap.v
Wrap SRL{16,32} too
2019-08-20 15:09:38 -07:00
abc_xc7_nowide.lut
Add _nowide variants of LUT libraries in -nowidelut flows
2019-06-26 10:23:29 -07:00
abc_xc7.box
Wrap LUTRAMs in order to capture comb/seq behaviour
2019-08-20 14:49:11 -07:00
abc_xc7.lut
Simplify comment
2019-06-17 19:14:41 -07:00
arith_map.v
Instead of MUXCY/XORCY use CARRY4 (with timing)
2019-05-21 16:19:45 -07:00
brams_init.py
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
cells_map.v
Use abc_{map,unmap,model}.v
2019-08-20 12:39:11 -07:00
cells_sim.v
Remove SRL* delays from cells_sim.v
2019-08-20 18:14:40 -07:00
cells_xtra.sh
Merge remote-tracking branch 'origin/master' into xaig
2019-06-25 09:33:11 -07:00
cells_xtra.v
Merge remote-tracking branch 'origin/master' into xaig
2019-06-25 09:33:11 -07:00
ff_map.v
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
2019-07-11 21:13:12 +02:00
lut_map.v
Really permute Xilinx LUT mappings as default LUT6.I5:A6
2019-06-18 11:48:48 -07:00
lutrams_map.v
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
lutrams.txt
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
Makefile.inc
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 17:36:14 -07:00
mux_map.v
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
synth_xilinx.cc
Cleanup techmap in map_luts
2019-08-20 17:59:31 -07:00
xc6s_brams_bb.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc6s_brams_map.v
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
xc6s_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_brams_bb.v
Add BRAM arrival times
2019-08-19 12:46:35 -07:00
xc7_brams_map.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00