github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-25 11:56:22 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/techlibs/gowin
History
YRabbit 79c5a06673 gowin: Fix SDP write enable port. 
This primitive does not have a separate WRE port, so we regulate writing
using Clock Enable.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-01-30 17:06:59 +10:00
..
arith_map.v
gowin: Fix X output of $alu techmap
2023-05-01 17:56:41 +02:00
brams_map.v
gowin: Fix SDP write enable port.
2024-01-30 17:06:59 +10:00
brams.txt
gowin: Change BYTE ENABLE handling.
2024-01-27 17:19:49 +10:00
cells_map.v
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
cells_sim.v
gowin: fix abc9 attributes and specify blocks
2023-10-04 00:16:10 +01:00
cells_xtra.py
gowin: Add all the primitives.
2023-04-22 17:10:53 +10:00
cells_xtra.v
gowin: Add all the primitives.
2023-04-22 17:10:53 +10:00
lutrams_map.v
gowin: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams.txt
gowin: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Makefile.inc
gowin: Add all the primitives.
2023-04-22 17:10:53 +10:00
synth_gowin.cc
Enable bram for Gowin
2023-12-03 10:17:28 +01:00