Emil J. Tywoniak 68bb5c6b94 signorm: disable in passes that use swap_names

2026-05-22 18:37:58 +02:00

..

common

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

pp3

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

qlf_k6n10f

Drop timestamp in generate_bram_types_sim.py

2024-10-30 08:47:18 +01:00

.gitignore

add dsp inference

2023-12-04 15:52:02 +01:00

Makefile.inc

add ioff inference for qlf_k6n10f

2025-01-24 21:17:15 +01:00

ql_bram_merge.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_bram_types.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_dsp_io_regs.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_dsp_macc.cc

Fixing couple more conversion errors

2026-05-14 15:58:58 +02:00

ql_dsp_macc.pmg

ql_dsp_macc: Tune DSP inference code

2023-12-04 15:52:02 +01:00

ql_dsp_simd.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_ioff.cc

signorm: disable in passes that use swap_names

2026-05-22 18:37:58 +02:00

synth_quicklogic.cc

Add check before flatten in synth_*.

2026-05-05 14:06:58 +02:00