Clifford Wolf 7d1088afc4 Add missing .gitignore ...

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2018-12-06 07:29:37 +01:00

..

.gitignore

Add missing .gitignore

2018-12-06 07:29:37 +01:00

run-test.sh

Support for SystemVerilog interfaces as a port in the top level module + test case

2018-10-20 11:58:25 +02:00

runone.sh

Support for SystemVerilog interfaces as a port in the top level module + test case

2018-10-20 11:58:25 +02:00

svinterface1_ref.v

Basic test for checking correct synthesis of SystemVerilog interfaces

2018-10-18 22:40:53 +02:00

svinterface1_tb.v

Basic test for checking correct synthesis of SystemVerilog interfaces

2018-10-18 22:40:53 +02:00

svinterface1.sv

Basic test for checking correct synthesis of SystemVerilog interfaces

2018-10-18 22:40:53 +02:00

svinterface_at_top_ref.v

Support for SystemVerilog interfaces as a port in the top level module + test case

2018-10-20 11:58:25 +02:00

svinterface_at_top_tb_wrapper.v

Support for SystemVerilog interfaces as a port in the top level module + test case

2018-10-20 11:58:25 +02:00

svinterface_at_top_tb.v

Support for SystemVerilog interfaces as a port in the top level module + test case

2018-10-20 11:58:25 +02:00

svinterface_at_top_wrapper.v

Support for SystemVerilog interfaces as a port in the top level module + test case

2018-10-20 11:58:25 +02:00

svinterface_at_top.sv

Support for SystemVerilog interfaces as a port in the top level module + test case

2018-10-20 11:58:25 +02:00