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YosysHQ.yosys/backends/verilog
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whitequark e95a8ba763 write_verilog: dump $mem cell attributes. 
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
2020-02-06 16:22:42 +00:00
..
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
verilog_backend.cc
write_verilog: dump $mem cell attributes.
2020-02-06 16:22:42 +00:00