1
0
mirror of synced 2026-04-25 20:02:10 +00:00
Files
YosysHQ.yosys/tests/hana/test_simulation_shifter_left_8_test.v
Clifford Wolf 7764d0ba1d initial import
2013-01-05 11:13:26 +01:00

5 lines
103 B
Verilog

module test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT);
assign OUT = IN << SHIFT;
endmodule