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YosysHQ.yosys/techlibs/common
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Jannis Harder f728927307 Add builtin celltype $scopeinfo 
Only declares the cell interface, doesn't make anything use or
understand $scopeinfo yet.
2024-02-06 17:51:24 +01:00
..
.gitignore
…
abc9_map.v
techmap: Add support for [] wildcards in techmap_celltype.
2020-08-02 22:46:48 +02:00
abc9_model.v
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
abc9_unmap.v
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
adff2dff.v
Fix syntax error in adff2dff.v
2021-02-24 01:07:34 +01:00
cellhelp.py
…
cells.lib
…
cmp2lcu.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
cmp2lut.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
cmp2softlogic.v
techlibs: Add cmp2softlogic.v to common
2023-11-13 10:42:12 +01:00
dff2ff.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
gate2lut.v
Fix invalid verilog syntax
2020-03-14 14:33:44 +01:00
gen_fine_ffs.py
Add $aldff and $aldffe: flip-flops with async load.
2021-10-02 18:12:52 +02:00
Makefile.inc
techlibs: Add cmp2softlogic.v to common
2023-11-13 10:42:12 +01:00
mul2dsp.v
Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
pmux2mux.v
…
prep.cc
Run future as part of prep
2023-09-13 11:32:36 +02:00
simcells.v
Add $aldff and $aldffe: flip-flops with async load.
2021-10-02 18:12:52 +02:00
simlib.v
Add builtin celltype $scopeinfo
2024-02-06 17:51:24 +01:00
smtmap.v
Add smtmap.v describing the smt2 backend's behavior for undef bits
2022-10-20 15:48:18 +02:00
synth.cc
mult -> booth in synth.cc, to turn on use synth -booth
2023-09-08 16:44:59 -07:00
techmap.v
Add bitwise $bweqx and $bwmux cells
2022-11-30 18:24:35 +01:00