Clifford Wolf c10e96c9ec Start work on pre-processor for Verific SVA properties

2017-10-10 15:16:39 +02:00

..

ast

Turned a few member functions into const, esp. dumpAst(), dumpVlog().

2017-09-30 07:37:38 +03:00

blif

Increase maximum LUT size in blifparse to 12 bits

2017-09-27 15:27:42 +02:00

ilang

Added avail params to ilang format, check module params in 'hierarchy -check'

2016-10-22 11:05:49 +02:00

json

Parse reals as string in JSON front-end

2017-09-26 14:37:03 +02:00

liberty

Added liberty parser support for types within cell decls

2016-09-23 13:53:23 +02:00

verific

Start work on pre-processor for Verific SVA properties

2017-10-10 15:16:39 +02:00

verilog

Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution

2017-09-30 06:39:07 +03:00

vhdl2verilog

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00