Robert O'Callahan e87bb65956 Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.

2026-01-23 01:14:35 +00:00

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choices

Merge pull request #4789 from YosysHQ/emil/sklansky-adder

2024-12-03 11:33:13 +01:00

.gitignore

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abc9_map.v

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abc9_model.v

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abc9_unmap.v

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adff2dff.v

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cellhelp.py

cellhelp.py: Cells can have tags

2024-10-15 07:35:41 +13:00

cmp2lcu.v

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cmp2lut.v

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cmp2softlogic.v

techlibs: Add cmp2softlogic.v to common

2023-11-13 10:42:12 +01:00

dff2ff.v

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gate2lut.v

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gen_fine_ffs.py

simcells: Apply group tags

2024-10-15 07:35:40 +13:00

Makefile.inc

sdc_expand, opensta: start

2025-11-19 15:20:50 +01:00

mul2dsp.v

Fix files with CRLF line endings

2021-06-09 12:16:33 +02:00

opensta.cc

opensta, sdc_expand: mark as experimental

2025-11-19 15:31:17 +01:00

opensta.h

opensta: refactor default command

2025-11-19 15:20:50 +01:00

pmux2mux.v

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prep.cc

Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.

2026-01-23 01:14:35 +00:00

sdc_expand.cc

opensta, sdc_expand: mark as experimental

2025-11-19 15:31:17 +01:00

simcells.v

Docs: Assert cell has group

2024-10-15 07:35:40 +13:00

simlib.v

added SIMLIB_VERILATOR_COMPAT

2025-10-01 10:19:25 -07:00

smtmap.v

Add smtmap.v describing the smt2 backend's behavior for undef bits

2022-10-20 15:48:18 +02:00

synth.cc

read_verilog: add -relativeshare for synthesis reproducibility testing

2025-09-16 15:47:35 +02:00

techmap.v

techmap: map $alu to $fa instead of relying on extract_fa

2025-09-23 17:05:12 +02:00