github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-17 00:52:28 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/tests
History
Martin Povišer c4762d930e
Merge pull request #3930 from povik/verific-test-memsemantics 
verific: Add test of accurate semantics in memory inference
2023-09-20 11:46:42 +02:00
..
aiger
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
arch
put back previous test state, due to default change
2023-08-29 10:21:58 +02:00
asicworld
…
bind
Add support for parsing the SystemVerilog 'bind' construct
2021-07-16 09:31:39 -04:00
blif
Adding check for BLIF names command input plane size.
2022-08-21 23:18:20 -05:00
bram
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
errors
…
fmt
cxxrtl: include iostream when prints are used
2023-08-17 07:08:22 +02:00
fsm
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
hana
…
liberty
fix file rights
2023-05-17 13:39:57 +02:00
lut
…
memfile
…
memlib
More tests in memlib/generate.py
2023-02-21 05:23:15 +13:00
memories
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
opt
opt_expr: Fix 'signed X>=0' replacement for wide output ports
2023-08-01 13:50:12 +01:00
opt_share
tests: Parallelize
2020-09-21 15:07:02 +02:00
proc
proc_clean: only consider fully-defined switch operands too.
2023-08-12 02:46:31 +02:00
realmath
…
rpc
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
sat
Proper example code
2022-03-14 15:39:11 +01:00
select
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 15:35:05 -07:00
share
…
sim
Replace GNU specific invocation of basename(1) with the equivalent
2022-10-23 11:02:18 +13:00
simple
verilog: Support module-scoped task/function calls
2022-10-29 15:14:11 -04:00
simple_abc9
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
smv
…
sva
verific: Use new value change logic also for $stable of wide signals.
2022-05-11 13:05:27 +02:00
svinterfaces
Resolve package types in interfaces (#3658)
2023-02-12 18:25:39 -05:00
svtypes
Corrected handling of nested typedefs of struct/union
2023-07-20 23:39:44 -04:00
techmap
renamed passname to booth, replaced connect_sigSpecToWire with connect, updated test script
2023-09-08 15:34:56 -07:00
tools
support file locations containing spaces
2022-08-08 20:30:50 +02:00
unit
…
various
ast: use new format string helpers.
2023-08-11 04:46:52 +02:00
verific
verific: Add test of accurate semantics in memory inference
2023-09-18 16:37:15 +02:00
verilog
fix width of post-increment/decrement expressions
2023-09-18 23:46:06 -04:00
vloghtb
Use HTTPS for website links, gatecat email
2021-06-09 12:16:56 +02:00
xprop
xprop tests: Make iverilog invocation more portable
2023-02-13 16:54:11 +01:00
gen-tests-makefile.sh
Out of bounds checking for struct/union members
2023-02-19 23:25:08 +01:00