Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters

2025-09-01 23:34:42 +00:00

..

tests

Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.

2025-07-22 10:38:38 +00:00

abc9_model.v

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

arith_map.v

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

brams_defs.vh

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams_xc2v_map.v

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams_xc2v.txt

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams_xc3sda_map.v

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams_xc3sda.txt

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams_xc4v_map.v

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams_xc4v.txt

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams_xc5v_map.v

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams_xc6v_map.v

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams_xcu_map.v

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams_xcv_map.v

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

brams_xcv.txt

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

cells_map.v

Clearer diff for the all-x corner case

2025-04-07 07:55:30 +02:00

cells_sim.v

Update Xilinx cell definitions, fixes #3699

2023-03-23 09:44:36 +01:00

cells_xtra.py

Update Xilinx cell definitions, fixes #3699

2023-03-23 09:44:36 +01:00

cells_xtra.v

Update Xilinx cell definitions, fixes #3699

2023-03-23 09:44:36 +01:00

ff_map.v

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

lut_map.v

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

lutrams_xc5v_map.v

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

lutrams_xc5v.txt

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

lutrams_xcu.txt

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

lutrams_xcv_map.v

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

lutrams_xcv.txt

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

Makefile.inc

pmgen: Move passes out of pmgen folder

2025-01-31 15:18:28 +13:00

mux_map.v

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

synth_xilinx.cc

Remove .c_str() from stringf parameters

2025-09-01 23:34:42 +00:00

urams_map.v

URAM mapping : Fix port indexes according to Yosys warnings

2025-05-09 15:09:11 +02:00

urams.txt

URAM mapping : Add test for 2048 x 144b

2025-05-10 14:53:56 +02:00

xc3s_mult_map.v

…

xc3sda_dsp_map.v

…

xc4v_dsp_map.v

…

xc5v_dsp_map.v

…

xc6s_dsp_map.v

…

xc7_dsp_map.v

xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)

2020-09-23 09:15:24 -07:00

xcu_dsp_map.v

…

xilinx_dffopt.cc

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

xilinx_dsp48a.pmg

pmgen: Move passes out of pmgen folder

2025-01-31 15:18:28 +13:00

xilinx_dsp_cascade.pmg

pmgen: Move passes out of pmgen folder

2025-01-31 15:18:28 +13:00

xilinx_dsp_CREG.pmg

pmgen: Move passes out of pmgen folder

2025-01-31 15:18:28 +13:00

xilinx_dsp.cc

pmgen: Move passes out of pmgen folder

2025-01-31 15:18:28 +13:00

xilinx_dsp.pmg

pmgen: Move passes out of pmgen folder

2025-01-31 15:18:28 +13:00

xilinx_srl.cc

pmgen: Move passes out of pmgen folder

2025-01-31 15:18:28 +13:00

xilinx_srl.pmg

pmgen: Move passes out of pmgen folder

2025-01-31 15:18:28 +13:00