Clifford Wolf c4bdba78cb Added proper Design->addModule interface

2014-07-27 21:12:09 +02:00

..

bitpattern.h

Replaced more old SigChunk programming patterns

2014-07-24 23:10:58 +02:00

calc.cc

Strictly zero-extend unsigned A-inputs of shift operations

2014-03-06 11:53:37 +01:00

celltypes.h

Refactoring: Renamed RTLIL::Design::modules to modules_

2014-07-27 11:18:30 +02:00

compatibility.cc

Merged OSX fixes from Siesh1oo with some modifications

2014-03-13 12:48:10 +01:00

compatibility.h

Hotfix for kernel/compatibility.h

2014-03-13 12:55:15 +01:00

consteval.h

Refactoring: Renamed RTLIL::Module::cells to cells_

2014-07-27 01:51:45 +02:00

driver.cc

Added log_cmd_error_expection

2014-07-27 12:05:50 +02:00

log.cc

Added log_cmd_error_expection

2014-07-27 12:05:50 +02:00

log.h

Small improvements in PerformanceTimer API

2014-07-27 15:14:02 +02:00

modwalker.h

Refactoring: Renamed RTLIL::Module::cells to cells_

2014-07-27 01:51:45 +02:00

register.cc

Added support for here documents

2014-07-26 17:21:40 +02:00

register.h

Added support for here documents

2014-07-26 17:21:40 +02:00

rtlil.cc

Added proper Design->addModule interface

2014-07-27 21:12:09 +02:00

rtlil.h

Added proper Design->addModule interface

2014-07-27 21:12:09 +02:00

satgen.h

Changed users of cell->connections_ to the new API (sed command)

2014-07-26 15:58:23 +02:00

sigtools.h

Added SigPool::check(bit)

2014-07-27 15:38:02 +02:00

toposort.h

Added topological sorting to techmap

2014-07-27 16:43:39 +02:00