Ruben Undheim c50afc4246 Documentation improvements etc. ...

- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)

2018-10-13 20:34:44 +02:00

..

ast

Documentation improvements etc.

2018-10-13 20:34:44 +02:00

blif

Merge pull request #591 from hzeller/virtual-override

2018-08-15 14:05:38 +02:00

ilang

Add "make coverage"

2018-08-27 14:22:21 +02:00

json

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

liberty

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

verific

Improve Verific importer blackbox handling

2018-10-07 19:48:55 +02:00

verilog

Support for 'modports' for System Verilog interfaces

2018-10-12 21:11:48 +02:00