Marcelina Kościelnicka a3528649c8 memory_dff: Remove now-useless write port handling.

2021-03-08 20:16:29 +01:00

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.gitignore

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abc9_map.v

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abc9_model.v

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abc9_unmap.v

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adff2dff.v

Fix syntax error in adff2dff.v

2021-02-24 01:07:34 +01:00

cellhelp.py

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cells.lib

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cmp2lcu.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

cmp2lut.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

dff2ff.v

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gate2lut.v

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gen_fine_ffs.py

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Makefile.inc

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mul2dsp.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

pmux2mux.v

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prep.cc

memory_dff: Remove now-useless write port handling.

2021-03-08 20:16:29 +01:00

simcells.v

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simlib.v

Fix some trivial typos.

2021-01-03 23:52:59 -08:00

synth.cc

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techmap.v

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