13 lines
154 B
Verilog
13 lines
154 B
Verilog
module which_clock (x,y,q,d);
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input x,y,d;
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output q;
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reg q;
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always @ (posedge x or posedge y)
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if (x)
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q <= 1'b0;
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else
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q <= d;
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endmodule
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