This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-01-28 13:09:09 +00:00
Code
Issues
Releases
Wiki
Activity
Files
c7d128672846bfbbbb2cdf34ddcb65bd7f296a32
YosysHQ.yosys
/
frontends
/
verilog
History
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
..
.gitignore
Updated .gitignore file for ilang and verilog frontends
2014-10-15 01:14:38 +02:00
const2ast.cc
Fixed segfault on invalid verilog constant 1'b_
2015-09-22 08:13:09 +02:00
Makefile.inc
Adjust makefiles to work with out-of-tree builds
2015-08-12 15:04:44 +02:00
preproc.cc
Added support for macros as include file names
2016-11-28 14:50:17 +01:00
verilog_frontend.cc
Added "verilog_defines" command
2016-12-15 17:49:28 +01:00
verilog_frontend.h
Remember global declarations and defines accross read_verilog calls
2016-11-15 12:42:43 +01:00
verilog_lexer.l
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
verilog_parser.y
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00