Andrew Zonenberg 6fed2dc996 Merge https://github.com/cliffordwolf/yosys

2017-02-14 08:29:37 -08:00

..

cells_latch.v

greenpak4: Can now techmap inferred D latches (without set/reset or output inverter)

2016-12-10 18:46:36 +08:00

cells_map.v

Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet.

2016-12-05 21:22:41 -08:00

cells_sim.v

greenpak4: Added POUT to GP_COUNTx cells

2017-01-01 00:56:20 -08:00

gp_dff.lib

Fixed indenting in techlibs/greenpak4/gp_dff.lib

2016-03-29 13:44:14 +02:00

greenpak4_counters.cc

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

greenpak4_dffinv.cc

greenpak4: Added support for inferred input/output inverters on latches

2016-12-10 19:58:32 +08:00

Makefile.inc

greenpak4: Can now techmap inferred D latches (without set/reset or output inverter)

2016-12-10 18:46:36 +08:00

synth_greenpak4.cc

Fix double-call of log_pop() in synth_greenpak4

2017-02-14 11:57:54 +01:00