Wanda c36cf9c5ac write_verilog: avoid emitting empty cases. ...

The Verilog grammar does not allow an empty case.  Most synthesis tools
are quite permissive about this, but Quartus is not.  This causes
problems for amaranth with Quartus (see amaranth-lang/amaranth#931).

2023-10-08 01:11:30 +02:00

..

aiger

Merge pull request #3778 from jix/yw_clk2fflogic

2023-06-05 16:15:04 +02:00

blif

Slightly adjust the wording of "write_blif" help

2023-07-10 12:41:43 +02:00

btor

Use clk2fflogic attr on cells to track original FF names in witnesses

2023-05-25 12:48:02 +02:00

cxxrtl

cxxrtl: include iostream when prints are used

2023-08-17 07:08:22 +02:00

edif

Improve EDIF lib_cell_ports scan

2023-06-20 10:42:05 +02:00

firrtl

Mention 'bwmuxmap' in 'write_firrtl' help

2023-07-10 12:45:03 +02:00

intersynth

Intersynth URL

2021-06-09 12:42:52 +02:00

jny

Drop stray 'cellaigs.h' include from backend passes

2023-07-10 12:45:03 +02:00

json

Fixes for some of clang scan-build detected issues

2023-01-17 12:58:08 +01:00

rtlil

backends/rtlil: Do not shorten a value with z bits to 'x

2023-01-29 14:02:25 +01:00

simplec

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

smt2

Merge pull request #3902 from YosysHQ/krys/yw_join

2023-08-25 15:21:44 +02:00

smv

Add bwmuxmap pass

2022-11-30 18:50:53 +01:00

spice

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

table

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

verilog

write_verilog: avoid emitting empty cases.

2023-10-08 01:11:30 +02:00