dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
8 lines
174 B
Plaintext
8 lines
174 B
Plaintext
read_verilog red_or3x1_test.v
|
|
hierarchy -check -top test
|
|
|
|
techmap -map red_or3x1_map.v;;
|
|
|
|
splitnets -ports
|
|
show -prefix red_or3x1 -format dot -notitle -lib red_or3x1_cells.v
|