21 lines
562 B
Verilog
21 lines
562 B
Verilog
module MISTRAL_IB((* iopad_external_pin *) input PAD, output O);
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assign O = PAD;
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endmodule
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module MISTRAL_OB((* iopad_external_pin *) output PAD, input I);
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assign PAD = I;
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endmodule
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module MISTRAL_IO((* iopad_external_pin *) inout PAD, input I, input OE, output O);
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assign PAD = OE ? I : 1'bz;
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assign O = PAD;
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endmodule
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// Eventually, we should support clock enables and model them here too.
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// For now, CLKENA is used as a basic entry point to global routing.
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module MISTRAL_CLKBUF (
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input A,
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(* clkbuf_driver *) output Q
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);
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assign Q = A;
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endmodule |