Gary Wong ca7d94af99 verilog: improve string literal matching speed (fixes #5076) ...

Use a greedy regular expression to match input inside a string
literal, so that flex can accumulate a longer match instead of
invoking a rule for each individual character.

2025-05-31 22:38:44 -06:00

..

aiger

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

aiger2

aiger2: Clean debug print

2024-12-10 14:27:55 +01:00

ast

read_verilog: Mark struct as custom type

2025-05-26 12:19:33 +12:00

blif

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

json

fix handling of escaped chars in json backend and frontend

2022-02-18 17:13:09 +01:00

liberty

Liberty file caching with new libcache command

2025-04-03 13:39:35 +02:00

rpc

Fitting help messages to 80 character width

2022-08-24 10:40:57 +12:00

rtlil

read_rtlil: warn on assigns after switches in case rules

2024-11-21 22:41:13 +01:00

verific

verific: support single_bit_vector

2025-05-12 13:23:29 +02:00

verilog

verilog: improve string literal matching speed (fixes #5076)

2025-05-31 22:38:44 -06:00