Ethan Mahintorabi 805c302411 simplemap: Moves $pmux mapping from techmap.v to simple map ...

This Fixes the slow downs I observed in techmap.v, which we
attempted to fix via the simplify ast.h route originally. This
turned out to be rather complex though.

By moving $pmux to simplemap we can just avoid that code. My
test case now runs in 310s which is 40s faster than the baseline
change.

B:507898959
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>

2026-04-29 21:20:39 +00:00

..

choices

Merge pull request #4789 from YosysHQ/emil/sklansky-adder

2024-12-03 11:33:13 +01:00

.gitignore

Added first help messages for cell types

2015-10-14 16:27:42 +02:00

abc9_map.v

techmap: Add support for [] wildcards in techmap_celltype.

2020-08-02 22:46:48 +02:00

abc9_model.v

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

abc9_unmap.v

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

adff2dff.v

Fix syntax error in adff2dff.v

2021-02-24 01:07:34 +01:00

cellhelp.py

cellhelp.py: Cells can have tags

2024-10-15 07:35:41 +13:00

cmp2lcu.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

cmp2lut.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

cmp2softlogic.v

techlibs: Add cmp2softlogic.v to common

2023-11-13 10:42:12 +01:00

dff2ff.v

Add force_downto and force_upto wire attributes.

2020-05-19 01:42:40 +02:00

gate2lut.v

Fix invalid verilog syntax

2020-03-14 14:33:44 +01:00

gen_fine_ffs.py

simcells: Apply group tags

2024-10-15 07:35:40 +13:00

Makefile.inc

sdc_expand, opensta: start

2025-11-19 15:20:50 +01:00

mul2dsp.v

Fix files with CRLF line endings

2021-06-09 12:16:33 +02:00

opensta.cc

opensta, sdc_expand: mark as experimental

2025-11-19 15:31:17 +01:00

opensta.h

opensta: refactor default command

2025-11-19 15:20:50 +01:00

pmux2mux.v

Added techlibs/common/pmux2mux.v

2014-01-17 20:06:15 +01:00

prep.cc

Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.

2026-01-23 01:14:35 +00:00

sdc_expand.cc

opensta, sdc_expand: mark as experimental

2025-11-19 15:31:17 +01:00

simcells.v

simcells: $dffsr and derivatives undefine S&R in logic tables

2026-03-19 19:27:30 +01:00

simlib.v

fix $specrule port naming

2026-04-13 22:34:46 +02:00

smtmap.v

Add smtmap.v describing the smt2 backend's behavior for undef bits

2022-10-20 15:48:18 +02:00

synth.cc

Rename csa_tree to arith_tree.

2026-04-13 12:48:05 +02:00

techmap.v

simplemap: Moves $pmux mapping from techmap.v to simple map

2026-04-29 21:20:39 +00:00