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Xiretza 092e923330 verilog: fix buf/not primitives with multiple outputs

From IEEE1364-2005, section 7.3 buf and not gates:

> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.

yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.

2021-03-17 11:44:03 -04:00

ast.cc

sv: allow globals in one file to depend on globals in another

2021-03-12 11:22:41 -05:00

ast.h

verilog: Use proc memory writes in the frontend.

2021-03-08 20:16:29 +01:00

dpicall.cc

dpi: Support for chandle type

2021-01-23 22:24:31 +00:00

genrtlil.cc

verilog: Use proc memory writes in the frontend.