Marcelina Kościelnicka 107aad2cd2 show: Fix wire bit indexing. ...

Fixes #3078.

2021-11-12 15:09:58 +01:00

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cmds

show: Fix wire bit indexing.

2021-11-12 15:09:58 +01:00

equiv

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

fsm

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

hierarchy

verilog: use derived module info to elaborate cell connections

2021-10-25 18:25:50 -07:00

memory

FfData: some refactoring.

2021-10-07 04:24:06 +02:00

opt

gowin: widelut support (#3042)

2021-11-06 16:09:30 +01:00

pmgen

Make it work on all

2021-11-05 10:51:58 +01:00

proc

proc_dff: Emit $aldff.

2021-10-27 14:14:24 +02:00

sat

FfData: some refactoring.

2021-10-07 04:24:06 +02:00

techmap

Merge pull request #3077 from YosysHQ/claire/genlib

2021-11-10 20:02:34 +01:00

tests

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00