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YosysHQ.yosys/tests
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Patrick Urban 81964d6d6f synth_gatemate: Update pass 
* remove `write_edif` and `write_blif` options
* remove redundant `abc` call before muxcover
* update style
2021-11-13 21:53:25 +01:00
..
aiger
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
arch
synth_gatemate: Update pass
2021-11-13 21:53:25 +01:00
asicworld
…
bind
Add support for parsing the SystemVerilog 'bind' construct
2021-07-16 09:31:39 -04:00
blif
tests/blif: Add missing gitignore
2021-05-20 12:49:51 +02:00
bram
tests/bram: Do not generate write address collisions.
2021-03-08 16:53:03 +01:00
errors
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fsm
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
hana
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liberty
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
lut
Forgot to commit
2019-07-16 12:44:26 -07:00
memfile
Added 'set -e' into tests/memfile/run-test.sh
2020-02-06 10:45:40 -03:00
memories
Fix a regression from #3035.
2021-10-08 15:44:07 +02:00
opt
extract_reduce: Refactor and fix input signal construction.
2021-10-21 04:10:01 +02:00
opt_share
tests: Parallelize
2020-09-21 15:07:02 +02:00
proc
proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
2021-08-14 15:26:11 +02:00
realmath
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rpc
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
sat
assertpmux: Fix crash on unused $pmux output.
2021-02-22 23:30:28 +01:00
select
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 15:35:05 -07:00
share
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simple
verilog: use derived module info to elaborate cell connections
2021-10-25 18:25:50 -07:00
simple_abc9
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
smv
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sva
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svinterfaces
Add a test for interfaces on modules loaded on-demand
2021-07-14 22:54:50 -04:00
svtypes
sv: improve support for wire and var with user-defined types
2021-08-12 22:41:41 -06:00
techmap
dfflegalize: Add tests for aldff lowering.
2021-10-27 14:14:01 +02:00
tools
Fixes in vcdcd.pl for newer Perl versions
2021-10-19 10:56:43 +02:00
unit
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various
More deadname stuff
2021-06-09 12:40:33 +02:00
verilog
verilog: use derived module info to elaborate cell connections
2021-10-25 18:25:50 -07:00
vloghtb
Use HTTPS for website links, gatecat email
2021-06-09 12:16:56 +02:00
gen-tests-makefile.sh
tests: Parallelize
2020-09-21 15:07:02 +02:00