Clifford Wolf 9b0e7af6d7 Improve read_verilog debug output capabilities ...

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2019-03-21 20:52:29 +01:00

..

.gitignore

Add "make coverage"

2018-08-27 14:22:21 +02:00

const2ast.cc

Convert more log_error() to log_file_error() where possible.

2018-07-20 09:37:44 -07:00

Makefile.inc

Add "make coverage"

2018-08-27 14:22:21 +02:00

preproc.cc

Support SystemVerilog `` extension for macros

2018-05-17 00:09:56 -04:00

verilog_frontend.cc

Improve read_verilog debug output capabilities

2019-03-21 20:52:29 +01:00

verilog_frontend.h

Add "read_verilog -noassert -noassume -assert-assumes"

2018-09-24 20:51:16 +02:00

verilog_lexer.l

Fix handling of cases that look like sva labels, fixes #862

2019-03-10 16:27:18 -07:00

verilog_parser.y

Fix handling of cases that look like sva labels, fixes #862

2019-03-10 16:27:18 -07:00