Pepijn de Vos c2d358484f Gowin: deal with active-low tristate (#2971) ...

* deal with active-low tristate

* remove empty port

* update sim models

* add expected lut1 to tests

2021-08-20 21:21:06 +02:00

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arith_map.v

Use HTTPS for website links, gatecat email

2021-06-09 12:16:56 +02:00

brams_init.vh

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brams_map.v

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brams.txt

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cells_map.v

Gowin: deal with active-low tristate (#2971)

2021-08-20 21:21:06 +02:00

cells_sim.v

nexus: Add MULTADDSUB9X9WIDE sim model

2020-12-08 15:49:20 +00:00

cells_xtra.py

nexus: Add DSP simulation model

2020-11-18 10:21:17 +00:00

cells_xtra.v

nexus: Add DSP simulation model

2020-11-18 10:21:17 +00:00

dsp_map.v

nexus: DSP inference support

2020-11-20 08:45:55 +00:00

latches_map.v

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lrams_init.vh

nexus: Add LRAM inference

2020-12-07 13:27:17 +00:00

lrams_map.v

nexus: Add LRAM inference

2020-12-07 13:27:17 +00:00

lrams.txt

nexus: Add LRAM inference

2020-12-07 13:27:17 +00:00

lutrams_map.v

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lutrams.txt

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Makefile.inc

nexus: Add LRAM inference

2020-12-07 13:27:17 +00:00

parse_init.vh

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synth_nexus.cc

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2021-06-09 12:16:56 +02:00