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YosysHQ.yosys
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techlibs
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common
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Clifford Wolf
1202f7aa4b
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
..
blackbox.sed
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
Makefile.inc
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
pmux2mux.v
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
simcells.v
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
simlib.v
Bugfix in simlib.v for iverilog
2014-07-29 19:23:31 +02:00
techmap.v
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00