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YosysHQ.yosys/tests/various
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Claire Xenia Wolf d6e4d3f1ba Fix the tests we just broke 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-10 00:22:37 +01:00
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dynamic_part_select
Adding latch tests for shift&mask AST dynamic part-select enhancements
2020-06-09 15:17:01 -05:00
.gitignore
Add plugin.so.dSYM to .gitignore
2021-01-18 11:13:21 -07:00
abc9.v
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abc9.ys
abc9: uniquify blackboxes like whiteboxes (#2695)
2021-03-29 22:02:06 -07:00
async.sh
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
async.v
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attrib05_port_conn.v
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attrib05_port_conn.ys
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attrib07_func_call.v
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
attrib07_func_call.ys
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autoname.ys
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blackbox_wb.ys
blackbox: Include whiteboxed modules
2021-03-17 13:58:04 +00:00
bug1496.ys
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bug1531.ys
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bug1614.ys
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bug1710.ys
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bug1745.ys
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bug1781.ys
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bug1876.ys
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bug2014.ys
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chparam.sh
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const_arg_loop.sv
verilog: fix sizing of constant args for tasks/functions
2021-02-21 15:44:43 -05:00
const_arg_loop.ys
verilog: fix sizing of constant args for tasks/functions
2021-02-21 15:44:43 -05:00
const_func_block_var.v
Allow localparams in constant functions
2020-08-20 20:10:24 -04:00
const_func_block_var.ys
Allow blocks with declarations within constant functions
2020-07-25 10:16:12 -06:00
const_func.sv
verilog: fix sizing of constant args for tasks/functions
2021-02-21 15:44:43 -05:00
const_func.ys
verilog: fix sizing of constant args for tasks/functions
2021-02-21 15:44:43 -05:00
constcomment.ys
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constmsk_test.v
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constmsk_test.ys
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constmsk_testmap.v
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
countbits.sv
Add tests for $countbits
2021-02-26 12:28:58 -05:00
countbits.ys
Add tests for $countbits
2021-02-26 12:28:58 -05:00
deminout_unused.ys
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design1.ys
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design2.ys
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design.ys
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dynamic_part_select.ys
Removing trailing whitespace
2020-06-10 10:35:40 -05:00
elab_sys_tasks.sv
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elab_sys_tasks.ys
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equiv_opt_multiclock.ys
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equiv_opt_undef.ys
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
2020-07-27 18:36:13 +02:00
exec.ys
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fib_tern.v
verilog: support recursive functions using ternary expressions
2021-02-12 14:43:42 -05:00
fib_tern.ys
verilog: support recursive functions using ternary expressions
2021-02-12 14:43:42 -05:00
fib.v
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
fib.ys
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
func_port_implied_dir.sv
sv: complete support for implied task/function port directions
2020-12-31 16:17:13 -07:00
func_port_implied_dir.ys
sv: complete support for implied task/function port directions
2020-12-31 16:17:13 -07:00
gen_if_null.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
gen_if_null.ys
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
global_scope.ys
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gzip_verilog.v.gz
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gzip_verilog.ys
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help.ys
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hierarchy_defer.ys
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hierarchy_param.ys
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hierarchy.sh
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ice40_mince_abc9.ys
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integer_range_bad_syntax.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
integer_real_bad_syntax.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
logger_error.ys
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logger_nowarning.ys
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logger_warn.ys
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logger_warning.ys
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logic_param_simple.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
mem2reg.ys
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memory_word_as_index.data
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
memory_word_as_index.v
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
memory_word_as_index.ys
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
muxcover.ys
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muxpack.v
More deadname stuff
2021-06-09 12:40:33 +02:00
muxpack.ys
More deadname stuff
2021-06-09 12:40:33 +02:00
param_struct.ys
Support parameters using struct as a wiretype (#3050)
2021-11-16 10:59:54 +01:00
peepopt.ys
peepopt: Remove now-redundant dffmux pattern.
2020-08-07 13:21:34 +02:00
plugin.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
plugin.sh
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pmgen_reduce.ys
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pmux2shiftx.v
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pmux2shiftx.ys
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port_sign_extend.v
genrtlil: fix signed port connection codegen failures
2021-02-05 19:51:30 -05:00
port_sign_extend.ys
genrtlil: fix signed port connection codegen failures
2021-02-05 19:51:30 -05:00
primitives.ys
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printattr.ys
printattrs: Add test.
2020-05-27 08:00:00 +00:00
rand_const.sv
Allow combination of rand and const modifiers
2021-01-21 08:42:05 -07:00
rand_const.ys
Allow combination of rand and const modifiers
2021-01-21 08:42:05 -07:00
reg_wire_error.sv
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reg_wire_error.ys
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run-test.sh
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
scratchpad.ys
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script.ys
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sformatf.ys
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shregmap.v
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
shregmap.ys
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signed.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
signext.ys
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sim_const.ys
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specify.v
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specify.ys
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src.ys
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sta.ys
sta: very crude static timing analysis pass
2021-11-25 17:20:27 +01:00
submod_extract.ys
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submod.ys
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sv_defines_dup.ys
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sv_defines_mismatch.ys
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sv_defines_too_few.ys
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sv_defines.ys
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sv_implicit_ports.sh
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svalways.sh
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wreduce.ys
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write_gzip.ys
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xaiger.ys
xaiger: add testcase
2020-05-24 08:48:23 -07:00