5 lines
147 B
Plaintext
5 lines
147 B
Plaintext
read_verilog example.v
|
|
synth_xilinx -top example -family xc6s
|
|
iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I
|
|
write_edif -pvector bra example.edif
|